/* mga.h - minimal access to the GXT120P (Matrox MGA-1164SG) through the
 * AIX 4.3 RCM, from an ordinary user process. X must not be running.
 * Claude Opus 5.5, 2026-10-13. */
#ifndef MGA_H
#define MGA_H

#define FB_OFFSET   0x800000    /* framebuffer = register base + 8 MB (from loadddx) */
#define VRAM_SIZE   0x200000    /* 2 MB: two NEC D481850 SGRAMs */

/* drawing engine registers (MGA-1064SG/1164SG numbering) */
#define DWGCTL      0x1c00
#define MACCESS     0x1c04
#define ZORG        0x1c0c
#define PLNWT       0x1c1c
#define BCOL        0x1c20
#define FCOL        0x1c24
#define XYSTRT      0x1c40
#define XYEND       0x1c44
#define SGN         0x1c58
#define AR0         0x1c60
#define AR1         0x1c64
#define AR2         0x1c68
#define AR3         0x1c6c
#define AR4         0x1c70
#define AR5         0x1c74
#define AR6         0x1c78
#define CXBNDRY     0x1c80
#define FXBNDRY     0x1c84
#define YDSTLEN     0x1c88
#define PITCH       0x1c8c
#define YDST        0x1c90
#define YDSTORG     0x1c94
#define YTOP        0x1c98
#define YBOT        0x1c9c
#define CXLEFT      0x1ca0
#define CXRIGHT     0x1ca4
#define DR0         0x1cc0
#define DR2         0x1cc8
#define DR3         0x1ccc
#define DR4         0x1cd0
#define DR6         0x1cd8
#define DR7         0x1cdc
#define DR8         0x1ce0
#define DR10        0x1ce8
#define DR11        0x1cec
#define DR12        0x1cf0
#define DR14        0x1cf8
#define DR15        0x1cfc
#define GO          0x0100      /* add to a register to start the engine */
#define FIFOSTATUS  0x1e10
#define STATUS      0x1e14
/* RAMDAC (byte registers) */
#define PALWTADD    0x3c00
#define PALDATA     0x3c01
#define PIXRDMSK    0x3c02
#define PALRDADD    0x3c03

/* DWGCTL fields */
#define OP_TRAP     0x00000004
#define OP_BITBLT   0x00000008
#define AT_RPL      0x00000000
#define AT_RSTR     0x00000010
#define AT_ZI       0x00000030
#define AT_BLK      0x00000040
#define AT_I        0x00000070
#define Z_NOZCMP    0x00000000
#define Z_ZE        0x00000200
#define Z_ZLT       0x00000400
#define Z_ZLTE      0x00000500
#define SOLID       0x00000800
#define ARZERO      0x00001000
#define SGNZERO     0x00002000
#define SHFTZERO    0x00004000
#define BOP_COPY    0x000c0000
#define BFCOL       0x04000000

/* MACCESS pixel widths */
#define PW8         0
#define PW16        1
#define PW32        2

extern volatile unsigned char *mga_base;   /* registers */
extern volatile unsigned char *mga_fb;     /* framebuffer */
extern unsigned int mga_pdata[8];

int  mga_open(void);            /* 0 = ok */
void mga_close(void);
void mga_out(int reg, unsigned int v);
unsigned int mga_in(int reg);
void mga_outb(int reg, unsigned char v);
unsigned char mga_inb(int reg);
int  mga_fifo(int n);           /* wait for n free slots; 0 = ok, -1 = timeout */
int  mga_idle(void);            /* wait for engine idle; 0 = ok, -1 = timeout */
void mga_getpal(unsigned char *pal);        /* 768 bytes */
void mga_setpal(const unsigned char *pal);
double mga_now(void);           /* seconds, for timing */

#endif