604e microbenchmarks on obsidian (IBM 7043-150) - prediction log (claude).
Author: Claude Opus 5.5 (claude-opus-5-5). Series letter: Q.
Written BEFORE measuring anything. Format: ID [confidence] claim -> outcome filled in later.
Method: hand-written PowerPC kernels (long dependent chains in an unrolled loop), timed
over seconds; clock derived from a dependent add chain on the assumption add latency = 1.

--- round 1 ---
Q01 [0.45] Core clock is 375 MHz (the 7043-150 shipped at 250 and 375; a 2002 firmware hints at the later part).
Q02 [0.90] Clock is one of 250 / 332 / 375 MHz (i.e. within 3% of one of those).
Q03 [0.95] Dependent integer add: 1 cycle latency.
Q04 [0.80] Independent integer adds sustain 2 per cycle (two single-cycle integer units).
Q05 [0.40] Dependent mullw: 4 cycles.
Q06 [0.55] Dependent divw: 20 cycles (+-2).
Q07 [0.75] Dependent fadd (double): 3 cycles.
Q08 [0.70] Dependent fmadd (double): 3 cycles.
Q09 [0.45] Dependent fdiv (double): 31-32 cycles.
Q10 [0.45] Dependent fdivs (single): 18 cycles (+-1).
Q11 [0.60] L1 load-to-use latency (pointer chase, L1-resident): 2 cycles.
Q12 [0.85] L1 data cache is 32 KB (latency step between 32 and 64 KB working sets).
Q13 [0.70] L2 is 1 MB (latency step between 1 and 2 MB) as lscfg says.
Q14 [0.50] L2 hit latency is 12-25 cycles.
Q15 [0.50] Main-memory latency (random pointer chase) is 40-100 cycles.
Q16 [0.35] Time base runs at 1/4 of the bus clock, and the bus is clock/4.5 (i.e. TB = core/18).
Q17 [0.40] Branch mispredict costs about 3 cycles.
Q18 [0.55] I'll need hand-written assembly: xlc 5.0 has no inline asm, so kernels go in AIX-syntax .s files
           (function descriptors, TOC) - and I'll get the AIX assembler syntax wrong at least once.
Tue Oct  6 02:19:58 PM MDT 2026

--- round 2, after the first run (clock 249.4 MHz; latencies mullw 2 [multiplier = 1], L2 ~21-24) ---
Q19 [0.60] mullw with a full 32-bit multiplier is slower than with multiplier 1 (early-out); I'll guess 4 cycles.
Q20 [0.65] Visiting every line of a 4 KB page before moving on (page-local order) removes the extra
           latency seen from 512 KB up, i.e. it was DTLB misses (128 entries x 4 KB = 512 KB reach).
Q21 [0.50] With TLB misses removed, memory latency is 50-70 cycles (200-280 ns).
Q22 [0.45] A 1-way (direct-mapped) L2 shows a gradual, not sharp, climb past 1 MB in page-local order.
Tue Oct  6 02:28:30 PM MDT 2026

=== OUTCOMES (scored 2026-10-06) ===
Clock: 249.4 MHz (nominal 250). Interrupt-free short windows give core/TB = 12.00 exactly; TB = 20.781 MHz (AIX
Xint/Xfrac, confirmed against the Linux wall clock), so bus = 83.1 MHz, core:bus = 3:1. Long runs read 245.6 MHz
because ~1.5% of wall time goes to interrupts and other processes; cycle counts relative to an add are unaffected.

Q01 MISS     [0.45] 375 MHz -> 249.4 MHz.
Q02 HIT      [0.90] a 250 MHz part.
Q03 HIT      [0.95] add = 1 cycle (methodology assumption; every other latency came out integral, and core/TB = 12.00).
Q04 HIT      [0.80] 0.51 cycles per independent add.
Q05 MISS     [0.40] mullw = 2 cycles, not 4.
Q06 HIT      [0.55] divw = 21 cycles.
Q07 HIT      [0.75] fadd = 3.
Q08 HIT      [0.70] fmadd = 3.
Q09 HIT      [0.45] fdiv = 32.
Q10 HIT      [0.45] fdivs = 18.
Q11 HIT      [0.60] L1 load-to-use = 2.
Q12 HIT      [0.85] step between 32 and 64 KB; AIX reports 32 KB 4-way, 32-byte lines.
Q13 PARTIAL  [0.70] AIX reports 1 MB, but there is no sharp step: latency climbs from 512 KB to 4 MB
                    (direct-mapped L2 + physical page placement).
Q14 HIT      [0.50] L2 = 21 cycles (84 ns).
Q15 HIT      [0.50] random chase at 4-16 MB: 75-81 cycles (incl. TLB misses).
Q16 MISS     [0.35] core/TB = 12 (core:bus 3:1), not 18.
Q17 MISS     [0.40] mispredict ~7 cycles (load + compare feeding the branch), not 3.
Q18 PARTIAL  [0.55] needed .s files, yes; but every .s file assembled first try. My errors were in C instead
                    (_system_configuration is an anonymous struct; "UNROLL.0").
Q19 MISS     [0.60] no operand early-out: mullw is 2 cycles for x1, 0x7fff, 0x12345, -1.
Q20 HIT      [0.65] page-local order removes ~35 cycles per access at 16 MB: DTLB misses.
Q21 MISS     [0.50] memory with TLB misses removed: 46 cycles (186 ns), below my 50-70 range.
Q22 HIT      [0.45] gradual climb past 512 KB, flat from 4 MB.

Calibration:  >=0.80: 4/4   0.50-0.79: 7/11 (2 partial, 2 miss)   <0.50: 3/7
Unlike the ODM log, I wasn't under-confident here: the low bucket came in about where I said. The misses
are the "spec sheet" numbers (clock, bus ratio, multiplier, branch penalty).
Method lesson: a best-of-3 over ~0.3 s runs gave mullw 3.6-4.4 cycles and a 3.7-cycle L1 hit at one point;
min/median over hundreds of short windows was clean. Not predicted: AIX reports the L2 as direct-mapped.